Latchup


By Steven H. Voldman

John Wiley & Sons

Copyright © 2007 John Wiley & Sons, Ltd
All right reserved.

ISBN: 978-0-470-01642-8


Chapter One

CMOS Latchup

1.1 CMOS LATCHUP

Latchup!

In this chapter, a brief overview of latchup is provided. We will provide a first quick look on what latchup is. As a starting point, this discussion will be followed by a summary of evolution, history, key innovations and patents. This chapter discusses the key innovations, contributions and patents associated with the process of understanding how to address the latchup issue in semiconductor technology. In addition, this chapter will provide the reader what are the sources of latchup, from pulses to particles; latchup issues associated with ionizing radiation events, as well as current and voltage excursions outside of the native current and voltage conditions of a technology, will be shown. In this discussion, the issue of technology scaling and how scaling leads to latchup concerns will be reviewed. When this chapter is completed, the following chapters will spiral backward into more depth, on each individual area from models, testing and tools.

1.1.1 CMOS Latchup-What is Latchup?

Latchup is a state where a semiconductor device undergoes a high-current state as a result of interaction between a pnp and an npn bipolar transistor. The pnp and npn transistors can be natural to the technology, or parasitic devices. In CMOS technology, these are typically parasitic devices. For each p-channel MOSFET (metal oxide semiconductor field effect transistor) device, there is a corresponding parasitic pnp element formed between the p-channel diffusion, the n-well and the substrate. For each n-channel MOSFET (NMOS) device, there is a corresponding parasitic npn element formed between the n-channel diffusion, the p-substrate and the n-well of the p-channel MOSFET. For each inverter gate, there are corresponding pnp and npn parasitic bipolar elements. Figure 1.1 shows an example of a cross section of a CMOS inverter circuit.

When interaction occurs between a pnp and an npn bipolar transistor, regenerative feedback between the two transistors can lead to electrical instability. This interaction between a three-region pnp and a three-region npn that share base and collector regions can be viewed as a four-region pnpn device. As a result of the feedback between the two transistors, there exist stable and unstable regions in the I-V characteristic. The I-V characteristic is an S-type I-V characteristic with both a low-current/high-voltage state and a high-current/low-voltage state (Figure 1.2). In an S-type I-V characteristic, there are multiple current states for a given voltage level; the state it chooses is a function of the circuit load line. It is 'off' in normal operation and can be triggered 'on' in a high-current state. In this state, it establishes a high current at a low-voltage, allowing a low impedance shunt. When the two transistors are coupled, the combined device acts as a four-region device of alternating p- and n-doped regions with three physical p-n metallurgical junctions, forming a pnpn structure.

Why are we concerned about latchup? When these parasitic pnpn elements undergo a high-current state, latchup can initiate thermal runaway and can be destructive. Latchup events can lead to destruction of a semiconductor chip, package or system. The current magnitude is such that typically the semiconductor silicon, aluminum and copper metallization fails, and sometimes the package materials melt. Note that another indicator of latchup is the package cracking, melting, delamination, separation and outgassing. Another clear indicator, on a system level, is smoke. In these cases, it is difficult to provide chip-level failure analysis due to the magnitude of the package and system damage. When the card smoke is evident, the module package is melted and the silicon chip is molten, this is a good indicator that latchup has occurred in your semiconductor chip.

Back to the semiconductor device level, conceptually the two transistors can be understood as a cross-coupled pnp and npn bipolar junction transistor (BJT) device, where the base of the pnp BJT device is the collector of the npn BJT device and the base of the npn is the collector of the pnp BJT device. The two cross-coupled devices can be represented as a four-region pnpn (Figure 1.3). This pnp-npn BJT coupling establishes regenerative feedback leading to the S-type I-V characteristic and causing the electrical instability that is observed as a negative resistance state (dI/dV < 0). It is this feature that makes this interaction a danger and an enabler of latchup.

Application of a positive bias on the emitter of the pnp element and a ground potential on the emitter of the npn element establishes a voltage across the pnpn. The positive voltage provides forward biasing of the emitter-base junctions of the pnp and npn transistors. The base-collector junction of the pnp (which is also the base-collector junction of the npn) is in a reverse-biased state. This prevents current flow from the anode of the pnpn to the cathode. As the voltage is increased, the voltage across the base-collector junction increases. This mode of operation is called the forward blocking state. In order for current to flow efficiently from the pnpn anode to the cathode, the base-collector junction must allow current to flow. For current continuity at the cross-coupled nodes, the collector current of the pnp transistor must equal the base current of the npn transistor, as well as the collector current of the npn transistor must equal the base current of the pnp transistor. Mathematically, the coupling is established through solving Kirchoff's current law at the base-collector nodes. In this form, the standard equations of bipolar transistors can be used to quantify the interaction and current in the pnpn structure. Hence, the two nodal equations can be expressed as

[I.sub.cp] = [I.sub.bn],

[I.sub.cn] = [I.sub.bp],

where [I.sub.cp] and [I.sub.cn] are the collector currents of the pnp and npn bipolar junction transistors, respectively, and likewise, [I.sub.bn] and [I.sub.bp] are the base currents of the npn and pnp bipolar junction transistors, respectively. The total current through the pnpn structure is equal to the emitter current of the pnp or npn bipolar transistor, [I.sub.ep] and [I.sub.en], respectively. From Kirchoff's current law in the transistor, the emitter current must equal the sum of the base and collector currents: I = [I.sub.ep] = [I.sub.cp] + [I.sub.bp].

From the coupling relationships, the current can be expressed as

I = [I.sub.ep] = [I.sub.cp] + [I.sub.cn] = [I.sub.bp] + [I.sub.bn] = [I.sub.cn] + [I.sub.bn] = [I.sub.en] = I.

Solving for the current as a function of the two collector current relationships, the collector current can be represented as a function of the emitter current:

[I.sub.cp] = [alpha][I.sub.ep] + [I.sub.cp0],

[I.sub.cn] = [alpha][I.sub.en] + [I.sub.cn0],

where the collector current is equal to the product of the collector-to-emitter transport factor [alpha] and the emitter current summed with the base-collector leakage. Solving for the current through the pnpn structure,

I = [I.sub.cp0] + [I.sub.cn0]/1 - ([alpha]n + [alpha]p).

From this analysis, it is clear that the current is infinite, when the denominator is equal to zero. This condition can be expressed as

[[alpha].sub.p] + [[alpha].sub.n] = 1.

This expression shows that when the sum of the collector-to-emitter gains is equal to unity, the current goes to infinity. This can also be expressed as a function of the bipolar transistor current gain b, substituting in for the collector-emitter transport,

I = [I.sub.cp0] + [I.sub.cn0]/1 - ([[beta].sub.n]/[[beta].sub.n] + 1 + [[beta].sub.p]/[[beta].sub.p] + 1,

where

[[alpha].sub.n] = [[beta].sub.n]/[[beta].sub.n] + 1,

[[alpha].sub.p] = [[beta].sub.p]/[[beta].sub.p] + 1.

In this form, when the denominator is equal to zero, the product of the bipolar current gains is equal to unity:

[[beta].sub.n][[beta].sub.p] = 1.

The pnpn current magnitude can be large given that the numerator is large, or if the denominator approaches zero.

Hence, from a simple derivation, it can be observed that the regenerative feedback between the parasitic pnp and the npn has a condition where a large current can be established between the power supply and the ground rail in an inverter circuit through the parasitics associated with the p- and the n-channel MOSFET transistor. The transport properties of the parasitic pnp and the npn are also involved, which are influenced by the semiconductor process and the chip design layout. As a result, latchup involves the chip architecture, the circuit layout, the circuit design and the semiconductor process.

What is the frequency of these parasitics in a modern semiconductor design? Today, in an advanced CMOS microprocessor with 200 million transistors, there are 100 million p-channel MOSFETs and 100 million n-channel MOSFETs. As a result, there are 100 million pnp and 100 million npn transistors. Hence, there are on the order of 100 million pnpn elements in a CMOS logic chip that contains 100 million inverter circuits.

Question: How many circuits does it take to initiate CMOS latchup? Answer: One.

As the number of circuits increases, the number of peripheral circuits and I/O circuits increases. In a CMOS chip with 200 million transistors, there may be on the order of 1000-10 000 interface circuits. It is likely that voltage and current events on the interface circuits can lead to latchup.

Question: How many peripheral circuits does it take to initiate CMOS latchup? Answer: One.

Yet, today, the number of products exhibiting latchup is a small minority of designs and applications. Hence, there must be a method or methods to diagnose and discriminate which parasitic pnpn structures are important, and which are not. Additionally, there are semiconductor process solutions, circuit solutions and system solutions.

1.1.2 CMOS Latchup-Why is Latchup Still an Issue?

A key question on CMOS latchup is the following-Why is latchup still a concern? There are many reasons why latchup is an issue in today's semiconductor chips. The reasons why is is a concern in some corporations differ based on the choices made in the semiconductor technology, latchup design strategy as well as the latchup methodology. The following is a list of why this issue reoccurs in semiconductor chips:

lack of characterization of parasitic devices;

lack of semiconductor process control of parasitic devices;

lack of dc and ac models of parasitic devices;

lack of parasitic devices in the circuit simulation;

lack of extraction, checking and verification of parasitic devices;

lack of tools addressing parasitic devices between devices, circuits and subfunctions;

lack of ground rules that sufficiently provide 100% coverage of design environment;

low business priority of addressing CMOS latchup, until it is a concern;

lack of educational training on CMOS latchup in university and college course work for circuit and layout design engineers and technicians;

education focus on the understanding of bipolar transistors and parasitic transistors;

lack of focus on latchup during semiconductor process and device design point definition;

lack of preservation of dimensional and electrical similitude of the lateral and vertical dimensions in the scaling of CMOS technology;

lack of awareness of the CMOS latchup technology scaling and making CMOS latchup technology part of the technology roadmap;

lack of semiconductor device and CMOS latchup design point cosynthesis;

isolation, well and substrate scaling;

new design methodologies in digital, mixed signal and RF designs;

nonnative voltages integrated into products well above the native-voltage CMOS latchup capability;

introduction of high-voltage CMOS (HVCMOS) integrated with low-voltage CMOS (LVCMOS) circuitry;

new issues associated with subsystem and system integration;

reversal of battery installation;

negative polarity on pins;

wire-bond mismatching in multichip power systems.

These are just some of the reasons why today CMOS latchup is not 'cured' and remains an issue in today's semiconductor chips. In this book, we will address many of these issues in the following chapters.

1.1.3 Early CMOS Latchup History

The first transistor, invented at Bell Labs in 1947, was not a CMOS transistor, but was a bipolar junction transistor device. At that time, an advantage of the bipolar junction transistor was the ability to manufacture it, as well as the speed of the transistor. One of the early advantages of the bipolar junction transistor was that it was not a surface device, but a bulk device. In 1955, Bell Labs manufactured and demonstrated the first metal oxide semiconductor field effect transistor. The MOSFET structure was proposed in 1930 by Lilienfeld and Heil, but was not manufactured successfully due to fixed and mobile positive charge issues. Fixed charge and mobile charge problems also remained a large issue in p-channel transistors, leading to the early implementation of n-channel MOSFET technology. CMOS had to wait for the p-channel MOSFET device to emerge while the development and research community continued to look for a solution to the oxide charge problem.

By the late 1960s, many manufacturers offered integrated circuits based on either a p-channel or an n-channel MOSFET device. CMOS was invented by RCA and was first demonstrated by Al Medwin at RCA's technology center in Somerville, New Jersey. The RCA Corporation called this technology COS/MOS, which stood for complementary symmetry metal oxide silicon. The first circuits using COS/MOS included a circuit that contained 13 transistors with a 15-V power supply.

Early interest in CMOS was also due to the potential for military and space applications. Publications in the 1960s by Kinoshita et al., Poll and Leavy and Dennehy et al. focused on the initiation of CMOS latchup in radiation environments.

CMOS latchup became of growing interest in the early 1970s as interest increased in the usage of CMOS for mainstream technology applications. Interest in CMOS continued in Sandia Laboratories and RCA. Gregory and Shafer, Gallace and Pujol and Barnes et al. of Sandia Laboratories focused on latchup as an impediment to the mainstream integration of CMOS. During the first development of RCA's COS/MOS, CMOS latchup was discovered by Gallace and Pujol. Ironically, the parasitic bipolar transistors unintentionally formed by the CMOS inverter switch impacted the introduction of CMOS. With the early problems of CMOS technology, most corporations began to focus on NMOS technology.

In this time frame, prior to mainstream introduction of CMOS, model development, guidelines and radiation implications were analyzed. Alexander et al. evaluated MOS model implications. Brucker evaluated the implications on CMOS and silicon-on-sapphire (SOS) memory. Coppage and Evans evaluated the characteristics of the destruction induced by CMOS latchup. Total dose characterization and other nuclear radiation effects were evaluated by London and Wang, Simons and Ricketts.

It was during the late 1970s that the focus on how to improve CMOS latchup using design techniques and process solutions was first addressed. From a practical perspective, application guidelines were released by Stephenson to address CMOS latchup guidelines. The focus shifted toward addressing CMOS latchup by screening, testing and selection processes. Sivo et al. focused on methods of latchup screening. Crowley et al. used radiation as a method of selection. In this time frame, the use of neutron irradiation for the prevention of CMOS latchup was proposed by Adams and Sokel. In this time frame, the use of recombination centers (e.g. using gold dopants) was demonstrated by Dawes and Derbenwick.

In many corporations, the first attempts to establish a mainstream CMOS technology for memory and logic development discovered the problem of latchup. Early developers of CMOS were hindered by the latchup problem, impeding the mainstream introduction of CMOS in the 1970s. In those time frames, MOSFET-based static read access memory (SRAM) introduced resistor-load NMOS cells and four-device NMOS cells, and avoided integration of p-channel MOSFETs into the network. As a result, CMOS logic was delayed until solutions to latchup were resolved.

(Continues...)



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